Tools I've built

• Statilyser

  A static analysis tool for HDL. Catches bugs in hardware descriptions before they reach simulation. Supports VHDL, verilog and system verilog

  statilyser.ardveriumlabs.com

• Garden of EDA

  A curated directory of open-source EDA tools spanning simulation, synthesis, verification, and FPGA/ASIC flows.

  garden-of-eda.com