A summary of my doctoral thesis
SRAM-FPGA
SRAM-based field programmable gate arrays (SRAM-FPGAs) are a class of programmable integrated circuits that use static random-access memory (SRAM) cells to configure their logic and routing resources. These devices play a pivotal role in digital computing owing to their inherent parallelism, high logic capacity and reconfigurability. These attributes have led to their widespread adoption in space missions, aerospace, medical devices, data centers, nuclear reactors and high-energy particle accelerators. In hazardous radiation environments, SRAM-FPGAs are valued not only for their high performance and cost-effectiveness but also for their ability to support design updates with minimal manual intervention and no physical hardware modifications.
Dependability Challenges
These devices,however, are vulnerable to single event upset (SEU), a radiation-induced error which inverts SRAM cell contents. Since the configuration memory, which stores the FPGA functionality and the routing information, is composed of SRAM cells, such changes can have catastrophic consequences in safety-critical applications. The continued CMOS scaling further exacerbates this problem through reduced feature size and increased volume of configuration bits. As devices shrink, they become more susceptible to multiple errors that weaken the traditional mitigation schemes. Moreover, the exponential growth in configurable elements increase the cost and complexity of validation techniques such as fault injection.
Addressing these dependability challenges in SRAM-FPGAs forms the core objective of this thesis. To achieve this, we introduce techniques to (1) detect failures in the scrubber, a widely used mitigation scheme for configuration memory (2) optimize fault injection to reduce experimental time and (3) identify vulnerable areas of the FPGA fabric to streamline dependability efforts.
Proposed Solutions
To detect scrubber failures, this work introduces two non-invasive, log-based frameworks: a Markov chain model for scrubber health monitoring, and AnoDe, a self-supervised failure detection system. They cater to varying levels of domain knowledge, with the former leveraging IP specifications and the latter requiring none, making them adaptable to diverse operational scenarios.
For optimizing fault injection, a Bayesian sampling framework is proposed to reduce the number of injections by integrating prior knowledge with the observed data. This method maintains the statistical confidence and the black-box nature of classical statistical fault injection while addressing the inflated sample size caused by parameter uncertainty.
To identify critical bits in the configuration memory, this thesis presents a guided fault injection strategy that leverages the inherent structure of the FPGA fabric. By exploiting the spatial locality of configuration bits, this approach significantly reduces the number of injections required to identify critical bits, thereby accelerating the process of vulnerability assessment and mitigation.
These approaches integrate seamlessly into existing fault injection setups and are particularly valuable in environments with limited access to radiation facilities. Collectively, the methods developed in this work advance the state of the art in SEU resilience and enable the broader adoption of commercial SRAM-FPGAs in safety-critical domains.
Papers
The thesis is built around seven research papers. The full thesis is available on the KTH DiVA portal.
- A Markovian Approach for Detecting Failures in the Xilinx SEM Core
- AnoDe: A Log-based Self-Supervised Framework to Detect Scrubber Failures in SRAM-FPGA
- Navigating the Challenges of Statistical Fault Injection in SRAM-FPGA
- Bayesian Sampling Framework for Improved Statistical Fault Injection
- Guided Fault Injection Strategy for Rapid Critical Bit Detection in Radiation-Prone SRAM-FPGA
- Predictive Modeling of Multi-Bit Upsets for Emulated Fault Injection
- Exploring the Potential of LSTM on Emulating Multiple-bit Fault Injection in SRAM-FPGA
Defense presentation
The slide deck from my doctoral defense
